As the demand for more complex functions and higher performance in integrated circuits increases, it becomes necessary to reduce parasitic resistances of device structures as much as possible. One method which has been developed to reduce parasitic resistances involves self-aligned silicide (so called "SALICIDE") device structures. The conventional self-aligned silicide insulated-gate field-effect transistor (IGFET) device structures include silicide layers formed over source/drain junction regions and transistor polysilicon gate regions. Silicide has a much lower sheet resistance than doped polysilicon normally used to form the IGFET gate regions. As a result, when the gate regions are silicided, the low resistance silicide layer shunts the higher resistance polysilicon layer. Accordingly, the silicided gate structures reduce the parasitic gate resistance and IGFET gate propagation delay due to this silicide shunting effect. Moreover, the silicided source/drain junctions also have smaller parasitic resistance values and, as a result, allow larger extrinsic device transconductance values.
The silicidation process on source/drain junctions, however, can cause some possible problems in advanced sub-0.5 micron technologies. Because silicidation consumes a portion of the underlying silicon, deeper source/drain junction regions are typically required to prevent excessive junction leakage. However, deeper source/drain junctions result in increased short-channel effects such as drain-induced barrier lowering (DIBL) and punch-through leakage. Other problems include higher junction leakage, source/drain junction dopant loss to the silicide, and bridging problems leading to device manufacturing yield loss.